1. Field of the Invention
This invention relates to electronic circuitry, and more particularly to memory write-recovery circuitry for static random access memories.
2. Description of the Prior Art
Digital memory circuits typically have a plurality of memory cells connected in rows and columns with bit lines and complementary bit lines connecting the cells in a column. Also on the chip are circuits for writing data to and reading data from the memory cells. In writing data a voltage transient several volts in magnitude is introduced into a bit line, while in reading data a transient of about 90 mV is sensed. Because the voltage transient of a write operation is so much larger than the transient of a read operation, in a read-follows-write sequence the write signal must be almost complete dissipated before the small differential voltage can be read. The delay waiting for the write transient to dissipate extends the access time, that is, the time to read following a write operation.
Write-recovery circuits are known which hasten removal of the transients following a write operation. A write-recovery circuit "recovers" or forces the bit lines in the column to which data last was written to be within a desired voltage differential to permit reading. During a write operation, a write recovery circuit holds all bit lines at a high potential, other than the one-bit line pulled low during the write. After the write operation, the recovery circuit pulls the low bit line up to the high potential.
A typical prior art write-recovery circuit is shown in FIG. 1. During a read operation, the circuit shown in FIG. 1 places all bit lines at the common high potential. The circuit detects when a write transition occurs, then generates an address transition pulse (ATP) which pulls the low bit line back up to the high potential. In the circuit shown in FIG. 1, transistors M1 and M2 short the bit lines to the high potential, Vcc, during a read operation. An ATP generator G1 activates transistors M3, M4 and M5 when an address transition occurs. Transistors M3 and M5 pull-up or "recover" the appropriate bit line Bit or Bitb, and at the same time transistor M4 acts as a shunt to equalize the differential voltage between Bit and Bitb. Because one of the bit lines is already at the high potential, transistor M4 causes both bit lines to be within a small voltage differential of one another, enabling a read operation to be performed.
Prior art circuits of the type shown in FIG. 1 have several disadvantages. Transistors M3 and M5 are relatively slow MOS devices resulting in relatively long recovery times. Furthermore, the width of the ATP pulse is critical: too narrow a pulse causes poor recovery and extended access time; too wide a pulse wastes time, slowing the entire memory system. In general, prior art circuits of the type shown in FIG. 1 are only capable of recovering in approximately 3 nS, and produce approximately 30 nS system access time.